Видео ютуба по тегу Risc-V Soc

ESP32-C5: First RISC-V SoC with Dual-band Wi-Fi 6, BLE 5, and 802.15.4 for Advanced Connectivity

ESP32-C5: First RISC-V SoC with Dual-band Wi-Fi 6, BLE 5, and 802.15.4 for Advanced Connectivity
RISC-V was supposed to change everything—How's it going?

RISC-V was supposed to change everything—How's it going?
Linus Torvalds: RISC-V Repeating the Mistakes of Its Predecessors

Linus Torvalds: RISC-V Repeating the Mistakes of Its Predecessors
SBC MangoPi-MQ1 on SoC Allwinner D1s RISC-V. LCD Testing

SBC MangoPi-MQ1 on SoC Allwinner D1s RISC-V. LCD Testing
Building a RISC-V CPU from scratch.

Building a RISC-V CPU from scratch.
ESP32-C6-Touch-LCD-1.69,160MHz RISC-V AI SoC,Zigbee/Thread/BLE/Wi-Fi 6 #waveshare #esp32 #esp32c6

ESP32-C6-Touch-LCD-1.69,160MHz RISC-V AI SoC,Zigbee/Thread/BLE/Wi-Fi 6 #waveshare #esp32 #esp32c6
Milk-V Jupiter — лучший одноплатный компьютер с архитектурой RISC-V? | 8 ГБ ОЗУ, два гигабитных порта и мощь искусственного интеллекта!

Milk-V Jupiter — лучший одноплатный компьютер с архитектурой RISC-V? | 8 ГБ ОЗУ, два гигабитных порта и мощь искусственного интеллекта!
RISC-V 2025 Update

RISC-V 2025 Update
Iguana: An End-to-End Open-Source Linux-capable RISC-V SoC in 130nm CMOS

Iguana: An End-to-End Open-Source Linux-capable RISC-V SoC in 130nm CMOS
TETRISC SoC — Quad RISC-V Core Self-Adaptive High-Reliability ASIC from IHP GmbH

TETRISC SoC — Quad RISC-V Core Self-Adaptive High-Reliability ASIC from IHP GmbH
Unlocking Open Source RISC-V SoC Verification - Michael Gielda

Unlocking Open Source RISC-V SoC Verification - Michael Gielda
THEJAS64: India’s Homegrown RISC-V SoC Booting Full Linux!

THEJAS64: India’s Homegrown RISC-V SoC Booting Full Linux!
Porting seL4 to the RISC-V SoC | Toward a Secure and High-Performance RISC-V AI Platform

Porting seL4 to the RISC-V SoC | Toward a Secure and High-Performance RISC-V AI Platform
VEGA Microprocessors | India's first Indigenous multi-core RISC-V ISA based processor

VEGA Microprocessors | India's first Indigenous multi-core RISC-V ISA based processor
RISC-V Server SoC Standardization - Ved Shanbhogue, Rivos

RISC-V Server SoC Standardization - Ved Shanbhogue, Rivos
First proper version of the custom RISCV SoC

First proper version of the custom RISCV SoC
ASIL Level RISC-V Core Accelerates Automotive SoC Design - Jianying Peng, Nuclei System Technology

ASIL Level RISC-V Core Accelerates Automotive SoC Design - Jianying Peng, Nuclei System Technology
RISC-V SoC Coherency: Dealing with Unique RISC-V Coherency Issues - Adnan Hamid, Breker Verification

RISC-V SoC Coherency: Dealing with Unique RISC-V Coherency Issues - Adnan Hamid, Breker Verification
💻🧑‍🏫 Проектирование микроконтроллера на кристалле с процессором SERV | Учебное пособие по RISC-V ...

💻🧑‍🏫 Проектирование микроконтроллера на кристалле с процессором SERV | Учебное пособие по RISC-V ...
Webinar - Making the Raven chip: How to design a RISC-V SoC

Webinar - Making the Raven chip: How to design a RISC-V SoC